The invention concerns a single-gate or multiple-gate field-effect transistor (FET).
A bulk single-gate FET and a single-gate FET of the semiconductor-on-insulator type, respectively, are shown in longitudinal cross-section in FIGS. 1a and 1b, each having a source 40 and a drain 50 separated by a thickness of material with appropriate physical and electrical properties for the creation of an active channel between the source 40 and the drain 50 when the transistor is polarised, and a gate 20 located above the aforementioned thickness of material, and separated from this thickness of material by a fine layer of dielectric material so that, when the gate 20 is polarised, the electric field is applied to the thickness of material in a direction that is substantially perpendicular to the general plane of the dielectric layer 30, with the layer of dielectric material 30 thus creating a capacitance whose dielectric constant is that of the dielectric concerned (SiO2, for example). Here, the single-gate FET is supported by a stiffening substrate 300 which is used in particular of give mechanical strength to the assembly. In a possible alternative, as illustrated in FIG. 1b, a thick layer 200 of dielectric material is inserted between the stiffening substrate 300 and the single-gate FET, mainly to improve the electrical properties of the transistor, the latter then becoming a single-gate FET-on-insulator. Polarisation of the gate 20, and of the source 40 and the drain 50 will then create a zone of accumulation of the charge carriers, forming an active channel between the source 40 and the drain 50 when this polarisation is direct and is greater than a determined voltage threshold, as well as a zone of inversion of the charge carriers in the part located under the channel. The single-gate FET is then conducting.
Regarding the multi-gate FETs, these have experienced considerable success in recent years because of the many advantages that they have, in particular in relation to the single-gate FETs, such as a reduction in short-channel effects (SCE), a gradient under the steep threshold, lack of body effect, and lower or even zero doping. These advantages are mainly brought about by the particular configuration of a multi-gate FET, which has a narrow active channel (separating the source from the drain) capable of being separated electrically from the bulk substrate.
A double-gate FET is illustrated in longitudinal cross-section and in cross-section in FIGS. 2a and 2b, respectively. This component has a source 40 and a drain 50 connected together electrically by an active channel 10, and two gates 20a and 20b located on either side of the active channel 10 (the upper gate being called the front gate 20a and the buried gate being called the back gate 20b) so as to apply an electric field to the channel 10 when they are polarised. The front gate 20a and the back gate 20b are substantially parallel to each other in order to create an approximately symmetrical electric field along the channel and perpendicular to the reference plane of the channel 10, here defined by a plane lying between the channel 10 and one of the two gates 20a and 20b. The gates 20a and 20b are each separated from the channel 10 by a layer of dielectric material 30a and 30b, thus creating a capacitance whose dielectric constant is that of the dielectric (such as SiO2). Here, the double-gate FET is supported by a stiffening substrate 300 which is used in particular to provide mechanical strength to the assembly. In a possible alternative, as illustrated in FIGS. 2a and 2b, a thick layer 200 of dielectric material is inserted between the stiffening substrate 300 and the double-gate FET, in particular to improve the electrical properties of the transistor, the latter then becoming a double-gate FET-on-insulator.
The application of two voltages, whether identical or not, VG and VG′, to each of the two gates 20a and 20b (according to a first configuration), or the application of a voltage, VG, to the front gate 20a and a connection to earth of the back gate 20b (in a second configuration) will then create at least one charge carrier accumulation zone or charge carrier inversion zone in the channel 10. From a threshold voltage, VS, applied to the gates 20a and 20b, a current will be able to flow between the source 40 and the drain 50 by means of the channel 10, the double-gate FET then being conducting.
Different designs of multi-gate FET are illustrated in FIGS. 3a to 3f. These are familiar to the previous designs. Note that, in order to simplify the explanation, these Figures show only the channel 10, the source 40, the drain 50 and the gates. The arrow appearing in each of the different Figures represents the direction of the current in the channel 10 (when VG>VS). Here, the support substrate is assumed to be located under the FETs shown.
FIG. 3a shows a double-gate planar FET whose gates 20a and 20b lie in parallel and on either side of the planes in which the current is flowing in the channel 10, with the FET here lying along its support substrate.
FIGS. 3b and 3c illustrate the double-gate FETs, in which the gates 20a and 20b lie in parallel and on either side of the flow planes of the current, with the FET of FIG. 3b extending in length in a direction that is substantially parallel to the surface of the support substrate, and the FET of FIG. 3c extending in length in a direction approximately perpendicular to the surface of the support substrate.
FIG. 3d represents a four-gate FET 20a, 20b, 20c, 20d, with the latter completely surrounding at least one part of the channel 10 along its length. This FET is also known as the GAA-FET (Gate-All-Around FET).
FIG. 3e represents a four-gate GAA-FET 20a, 20b, 20c and 20d, with the latter completely surrounding at least one part of the channel 10, and with the FET here being placed more vertically in relation to the substrate than the FET of FIG. 3d. 
FIG. 3f represents a FET called the Fin-FET, with three gates, the latter surrounding at least one part of the channel 10, two gates 20a and 20b extending in current flow planes as well as along the length of the channel 10.
Compared to single-gate FETs, the multi-gate FETs can attain transconductances that are twice as high, thanks to the particular properties of a narrow channel 10 surrounded by at least two gates. Despite the current performance of single- or multi-gate FETs, it would be desirable to increase the current within the channel 10. To this end, one could increase the section of the channel 10. However, with an excessively high thickness of the channel 10, the conventional gate or gates (as shown, for example, in FIGS. 1a and 3a to 3f) would not apply a sufficient field to cause an accumulation of all the charges in the channel 10. It is then not possible to take advantage of all of the mobile charges that may exist in such a thick channel l0.
Another tested solution is to have different structures of channel 10 such as a channel 10 in elastically stressed Si (thus having a substantially greater charge mobility in relation to elastically relaxed silicon) or stressed Si structures in SiGe, or a stressed SiGe structure in relaxed Si. However, these few channel structure proposals 10 can be implemented only at very thin channel thicknesses, because the layers of stressed material must not exceed a critical thickness beyond which the stresses lose their essentially elastic character. The magnitude of the current therefore remains very limited.